Up-to-date citation counts (provided by Google Scholar). List of patents granted.
2004
Andreas Doering; Marcel Waldvogel
Fast and Flexible CRC Calculation Artikel
In: IEE Electronics Letters, Bd. 40, Nr. 1, S. 10-11, 2004.
Abstract | BibTeX | Schlagwörter: CRC, FPGA, Network Processors | Links:
@article{Doering2004Fast,
title = {Fast and Flexible CRC Calculation},
author = {Andreas Doering and Marcel Waldvogel},
url = {https://netfuture.ch/wp-content/uploads/2004/doering04fast.pdf},
year = {2004},
date = {2004-01-01},
urldate = {1000-01-01},
journal = {IEE Electronics Letters},
volume = {40},
number = {1},
pages = {10-11},
abstract = {An algorithm for software or hardware implementation is presented, allowing fast computation of Cyclic Redundancy Checks with arbitrary polynomials and a high flexibility, such as updating of checksums after modifying data block parts with a known old checksum.},
keywords = {CRC, FPGA, Network Processors},
pubstate = {published},
tppubtype = {article}
}
2002
Florian Braun; John Lockwood; Marcel Waldvogel
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Networks Artikel
In: IEEE Micro, Bd. 22, Nr. 1, S. 66-74, 2002.
Abstract | BibTeX | Schlagwörter: Fast Routers, FPGA | Links:
@article{Braun2002Protocol,
title = {Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Networks},
author = {Florian Braun and John Lockwood and Marcel Waldvogel},
url = {https://netfuture.ch/wp-content/uploads/2002/braun02protocol.pdf},
year = {2002},
date = {2002-01-01},
urldate = {1000-01-01},
journal = {IEEE Micro},
volume = {22},
number = {1},
pages = {66-74},
abstract = { A library of layered protocol wrappers has been developed that process Internet packets in reconfigurable hardware. These wrappers can be used with a reprogrammable network platform called the Field Programmable Port Extender (FPX) to rapidly prototype hardware circuits for processing Internet packets. We present a framework to streamline and simplify the development of networking applications that process ATM cells, AAL5 frames, Internet Protocol (IP) packets and UDP datagrams directly in hardware.},
keywords = {Fast Routers, FPGA},
pubstate = {published},
tppubtype = {article}
}
2001
Florian Braun; John Lockwood; Marcel Waldvogel
Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware Konferenzbeitrag
In: Proceedings of IEEE Hot Interconnects 9, Stanford, CA, USA, 2001.
Abstract | BibTeX | Schlagwörter: Fast Routers, FPGA | Links:
@inproceedings{Braun2001Layered,
title = {Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware},
author = {Florian Braun and John Lockwood and Marcel Waldvogel},
url = {https://netfuture.ch/wp-content/uploads/2001/braun01layered.pdf},
year = {2001},
date = {2001-08-01},
urldate = {1000-01-01},
booktitle = {Proceedings of IEEE Hot Interconnects 9},
address = {Stanford, CA, USA},
abstract = { A library of layered protocol wrappers has been developed that process Internet packets in reconfigurable hardware. These wrappers can be used with a reprogrammable network platform called the Field Programmable Port Extender (FPX) to rapidly prototype hardware circuits for processing Internet packets. We present a framework to streamline and simplify the development of networking applications that process ATM cells, AAL5 frames, Internet Protocol (IP) packets and UDP datagrams directly in hardware.},
keywords = {Fast Routers, FPGA},
pubstate = {published},
tppubtype = {inproceedings}
}
Florian Braun; John Lockwood; Marcel Waldvogel
Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware Forschungsbericht
Washington University in St. Louis Nr. WUCS-01-10, 2001.
BibTeX | Schlagwörter: Fast Routers, FPGA
@techreport{Braun2001Layered-techreport,
title = {Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware},
author = {Florian Braun and John Lockwood and Marcel Waldvogel},
year = {2001},
date = {2001-01-01},
urldate = {1000-01-01},
number = {WUCS-01-10},
institution = {Washington University in St. Louis},
keywords = {Fast Routers, FPGA},
pubstate = {published},
tppubtype = {techreport}
}
Florian Braun; Marcel Waldvogel; John Lockwood
OBIWAN — An Internet Protocol Router in Reconfigurable Hardware Forschungsbericht
Washington University in St. Louis Nr. WU-CS-01-11, 2001.
BibTeX | Schlagwörter: Fast Routers, FPGA
@techreport{Braun2001OBIWAN-techreport,
title = {OBIWAN -- An Internet Protocol Router in Reconfigurable Hardware},
author = {Florian Braun and Marcel Waldvogel and John Lockwood},
year = {2001},
date = {2001-01-01},
urldate = {1000-01-01},
number = {WU-CS-01-11},
institution = {Washington University in St. Louis},
keywords = {Fast Routers, FPGA},
pubstate = {published},
tppubtype = {techreport}
}
Florian Braun; John Lockwood; Marcel Waldvogel
Reconfigurable Router Modules Using Network Protocol Wrappers Konferenzbeitrag
In: Field-Programmable Logic and Applications (FPL), S. 254–263, Belfast, Northern Ireland, 2001.
Abstract | BibTeX | Schlagwörter: Fast Routers, FPGA | Links:
@inproceedings{Braun2001Reconfigurable,
title = {Reconfigurable Router Modules Using Network Protocol Wrappers},
author = {Florian Braun and John Lockwood and Marcel Waldvogel},
url = {https://netfuture.ch/wp-content/uploads/2001/braun01reconfigurable.pdf},
year = {2001},
date = {2001-01-01},
urldate = {1000-01-01},
booktitle = {Field-Programmable Logic and Applications (FPL)},
pages = {254--263},
address = {Belfast, Northern Ireland},
abstract = { A library of layered protocol wrappers has been developed that process Internet packets in reconfigurable hardware. These wrappers can be used with a reprogrammable network platform called the Field Programmable Port Extender (FPX) to rapidly prototype hardware circuits for processing Internet packets. We present a framework to streamline and simplify the development of networking applications that process ATM cells, AAL5 frames, Internet Protocol (IP) packets and UDP datagrams directly in hardware. },
keywords = {Fast Routers, FPGA},
pubstate = {published},
tppubtype = {inproceedings}
}
2000
Marcel Waldvogel
Fast Longest Prefix Matching: Algorithms, Analysis, and Applications Promotionsarbeit
ETH Zürich, 2000.
BibTeX | Schlagwörter: Fast Routers, FPGA
@phdthesis{Waldvogel2000Fasta,
title = {Fast Longest Prefix Matching: Algorithms, Analysis, and Applications},
author = {Marcel Waldvogel},
year = {2000},
date = {2000-05-01},
urldate = {1000-01-01},
number = {13266},
school = {ETH Zürich},
keywords = {Fast Routers, FPGA},
pubstate = {published},
tppubtype = {phdthesis}
}
