General audience texts
Besides the scholarly publications listed below, I have written many texts in English and German. My more notable German texts appeared by DNIP.ch. I also maintain document collections intended for a broad audience:
Scholarly publications
Up-to-date citation counts (provided by Google Scholar). List of patents granted.
2004
Andreas Doering; Marcel Waldvogel
Fast and Flexible CRC Calculation Journal Article
In: IEE Electronics Letters, vol. 40, no. 1, pp. 10-11, 2004.
Abstract | BibTeX | Tags: CRC, FPGA, Network Processors | Links:
@article{Doering2004Fast,
title = {Fast and Flexible CRC Calculation},
author = {Andreas Doering and Marcel Waldvogel},
url = {https://netfuture.ch/wp-content/uploads/2004/doering04fast.pdf},
year = {2004},
date = {2004-01-01},
urldate = {1000-01-01},
journal = {IEE Electronics Letters},
volume = {40},
number = {1},
pages = {10-11},
abstract = {An algorithm for software or hardware implementation is presented, allowing fast computation of Cyclic Redundancy Checks with arbitrary polynomials and a high flexibility, such as updating of checksums after modifying data block parts with a known old checksum.},
keywords = {CRC, FPGA, Network Processors},
pubstate = {published},
tppubtype = {article}
}
An algorithm for software or hardware implementation is presented, allowing fast computation of Cyclic Redundancy Checks with arbitrary polynomials and a high flexibility, such as updating of checksums after modifying data block parts with a known old checksum.
2003
Andreas Kind; Roman Pletka; Marcel Waldvogel
The Role of Network Processors in Active Networks Proceedings Article
In: Proceedings of IWAN 2003, pp. 18-29, Kyoto, Japan, 2003.
Abstract | BibTeX | Tags: Active Networks, Network Processors, Quality of Service, Security | Links:
@inproceedings{Kind2003Role,
title = {The Role of Network Processors in Active Networks},
author = {Andreas Kind and Roman Pletka and Marcel Waldvogel},
url = {https://netfuture.ch/wp-content/uploads/2003/kind03role.pdf},
year = {2003},
date = {2003-12-01},
urldate = {1000-01-01},
booktitle = {Proceedings of IWAN 2003},
pages = {18-29},
address = {Kyoto, Japan},
abstract = {Network processors (NPs) implement a balance between hardware and software that addresses the demand of performance and programmability in active networks (AN). We argue that this makes them an important player in the implementation and deployment of ANs. Besides a general introduction into the relationship of NPs and ANs, we describe the power of this combination in a framework for secure and safe capsule-based active code. We also describe the advantages of offloading AN control point functionality into the NP and how to execute active code in the data path efficiently. Furthermore, the paper reports on experiences about implementing active networking concepts on the IBM PowerNP network processor. },
keywords = {Active Networks, Network Processors, Quality of Service, Security},
pubstate = {published},
tppubtype = {inproceedings}
}
Network processors (NPs) implement a balance between hardware and software that addresses the demand of performance and programmability in active networks (AN). We argue that this makes them an important player in the implementation and deployment of ANs. Besides a general introduction into the relationship of NPs and ANs, we describe the power of this combination in a framework for secure and safe capsule-based active code. We also describe the advantages of offloading AN control point functionality into the NP and how to execute active code in the data path efficiently. Furthermore, the paper reports on experiences about implementing active networking concepts on the IBM PowerNP network processor.
Robert Haas; Clark Jeffries; Lukas Kencl; Andreas Kind; Bernard Metzler; Roman Pletka; Marcel Waldvogel; Laurent Freléchoux; Patrick Droz
Creating Advanced Functions on Network Processors: Experience and Perspectives Journal Article
In: IEEE Network, vol. 17, no. 4, pp. 46-54, 2003.
Abstract | BibTeX | Tags: Active Networks, Network Processors, Quality of Service, Replication | Links:
@article{Haas2003Creating,
title = {Creating Advanced Functions on Network Processors: Experience and Perspectives},
author = {Robert Haas and Clark Jeffries and Lukas Kencl and Andreas Kind and Bernard Metzler and Roman Pletka and Marcel Waldvogel and Laurent Freléchoux and Patrick Droz},
url = {https://netfuture.ch/wp-content/uploads/2003/haas03creating.pdf},
year = {2003},
date = {2003-01-01},
urldate = {1000-01-01},
journal = {IEEE Network},
volume = {17},
number = {4},
pages = {46-54},
abstract = {In this paper, we present five case studies of advanced networking functions that detail how a network processor (NP) can provide high performance and also the necessary flexibility compared with Application-Specific Integrated Circuits (ASICs). We first review the basic NP system architectures, and describe the IBM PowerNP architecture from a data-plane as well as from a control-plane point of view. We introduce models for the programmer's views of NPs that facilitate a global understanding of NP software programming. Then, for each case study, we present results from prototypes as well as general considerations that apply to a wider range of system architectures. Specifically, we investigate the suitability of NPs for<ul><li>Quality of Service (active queue management and traffic engineering),</li><li>header processing (GPRS tunneling protocol),</li><li>intelligent forwarding (load balancing without flow disruption),</li><li>payload processing (code interpretation and just-in-time compilation in active networks), and protocol stack termination (SCTP).</li></ul>Finally, we summarize the key features as revealed by each case study, and conclude with remarks on the future of NPs.},
keywords = {Active Networks, Network Processors, Quality of Service, Replication},
pubstate = {published},
tppubtype = {article}
}
In this paper, we present five case studies of advanced networking functions that detail how a network processor (NP) can provide high performance and also the necessary flexibility compared with Application-Specific Integrated Circuits (ASICs). We first review the basic NP system architectures, and describe the IBM PowerNP architecture from a data-plane as well as from a control-plane point of view. We introduce models for the programmer’s views of NPs that facilitate a global understanding of NP software programming. Then, for each case study, we present results from prototypes as well as general considerations that apply to a wider range of system architectures. Specifically, we investigate the suitability of NPs for
- Quality of Service (active queue management and traffic engineering),
- header processing (GPRS tunneling protocol),
- intelligent forwarding (load balancing without flow disruption),
- payload processing (code interpretation and just-in-time compilation in active networks), and protocol stack termination (SCTP).
James Allen; Brian Bass; Claude Basso; Rick Boivie; Jean Calvignac; Gordon Davis; Laurent Freléchoux; Marco Heddes; Andreas Herkersdorf; Andreas Kind; Joe Logan; Mohammad Peyravian; Mark Rinaldi; Ravi Sabhikhi; Michael Siegel; Marcel Waldvogel
IBM PowerNP Network Processor: Hardware Software and Applications Journal Article
In: IBM Journal of Research and Development, vol. 47, no. 2/3, pp. 177-194, 2003.
Abstract | BibTeX | Tags: Fast Routers, Network Processors, Quality of Service | Links:
@article{Allen2003PowerNP,
title = {IBM PowerNP Network Processor: Hardware Software and Applications},
author = {James Allen and Brian Bass and Claude Basso and Rick Boivie and Jean Calvignac and Gordon Davis and Laurent Freléchoux and Marco Heddes and Andreas Herkersdorf and Andreas Kind and Joe Logan and Mohammad Peyravian and Mark Rinaldi and Ravi Sabhikhi and Michael Siegel and Marcel Waldvogel},
url = {https://netfuture.ch/wp-content/uploads/2003/allen03powernp.pdf},
year = {2003},
date = {2003-01-01},
urldate = {1000-01-01},
journal = {IBM Journal of Research and Development},
volume = {47},
number = {2/3},
pages = {177-194},
abstract = {Deep packet processing is migrating to the edges of service provider networks to simplify and speed up core functions. On the other hand, the cores of such networks are migrating to the switching of high-speed traffic aggregates, e.g., using switching with dense wavelength division multiplexing (DWDM). As a result, more services will need to be performed at the edges, both on behalf of the core and end users. Associated network equipment will therefore require high flexibility to support evolving high-level services as well as extraordinary performance to deal with the high packet rates. Whereas in the past network equipment were based either on general-purpose processors (GPPs) or application-specific integrated circuits (ASICs), favoring flexibility over speed or vice versa, the network processor approach achieves both flexibility and performance. The key advantage of network processors is that hardware-level performance is complemented by flexible software architecture. In this paper, we describe the IBM PowerNP&tm; NP4GS3 network processor and how it addresses these issues. Its hardware and software design characteristics and its comprehensive base operating software of this network processor make it well suited for a wide range of networking applications.},
keywords = {Fast Routers, Network Processors, Quality of Service},
pubstate = {published},
tppubtype = {article}
}
Deep packet processing is migrating to the edges of service provider networks to simplify and speed up core functions. On the other hand, the cores of such networks are migrating to the switching of high-speed traffic aggregates, e.g., using switching with dense wavelength division multiplexing (DWDM). As a result, more services will need to be performed at the edges, both on behalf of the core and end users. Associated network equipment will therefore require high flexibility to support evolving high-level services as well as extraordinary performance to deal with the high packet rates. Whereas in the past network equipment were based either on general-purpose processors (GPPs) or application-specific integrated circuits (ASICs), favoring flexibility over speed or vice versa, the network processor approach achieves both flexibility and performance. The key advantage of network processors is that hardware-level performance is complemented by flexible software architecture. In this paper, we describe the IBM PowerNP&tm; NP4GS3 network processor and how it addresses these issues. Its hardware and software design characteristics and its comprehensive base operating software of this network processor make it well suited for a wide range of networking applications.
