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Abstract
Terabit-per-second switches and routers are already beginning to be commercially available. However, numerous issues still exist in the design of very high-speed switches. Link speeds are now approaching, and exceeding, memory bandwidths, complicating buffer designs. In addition to very high-speed links and large switching capacities, future high-speed switches are expected to be able to support multiple classes of traffic with varying Quality-of-Service (QoS) requirements. This includes traffic classes with guaranteed throughput and bounded delay requirements. Input buffered architectures are being used to deal with memory bandwidth bottlenecks. New challenges arise in switch-matrix and flow-level scheduling. Challenges remain in packet classification. Multistage switching fabrics are being revisited. Network processors are opening new opportunities for supporting high-level capabilities including traffic management. In addition, standardization efforts for switch fabric interfaces are ongoing. Overall, this is an exciting time for switch developers and researchers.
BibTeX (Download)
@article{Christensen2002Issues,
title = {Issues and Trends in Terabit Switching},
author = {Ken Christensen and Marcel Waldvogel},
url = {http://www.sciencedirect.com/science/journal/01403664/25/6},
year = {2002},
date = {2002-01-01},
urldate = {1000-01-01},
journal = {Computer Communications},
volume = {25},
number = {6},
pages = {545--546},
abstract = {Terabit-per-second switches and routers are already beginning to be commercially available. However, numerous issues still exist in the design of very high-speed switches. Link speeds are now approaching, and exceeding, memory bandwidths, complicating buffer designs. In addition to very high-speed links and large switching capacities, future high-speed switches are expected to be able to support multiple classes of traffic with varying Quality-of-Service (QoS) requirements. This includes traffic classes with guaranteed throughput and bounded delay requirements. Input buffered architectures are being used to deal with memory bandwidth bottlenecks. New challenges arise in switch-matrix and flow-level scheduling. Challenges remain in packet classification. Multistage switching fabrics are being revisited. Network processors are opening new opportunities for supporting high-level capabilities including traffic management. In addition, standardization efforts for switch fabric interfaces are ongoing. Overall, this is an exciting time for switch developers and researchers.},
keywords = {Fast Routers},
pubstate = {published},
tppubtype = {article}
}
